Prerequisites

Some basic FPGA awareness would be an advantage, but is not required, although participants should have some knowledge of parallel processing concepts and/or parallel hardware. Most of the FPGA design work will be carried out in C++. Intermediate C++ programming experience is required.   AMD will provide remote access to AWS F1 cloud instances which will be enabled with Xilinx tools and devices.

Schedule

Total hours: 6 hours.

• Class 1: Thursday 16/3, 14:00hs to 17:00hs
• Class 2: Friday 17/3, 14:00hs to 17:00hs

Short Program

This course will introduce the Vitis Unified Software Platform environment for developing FPGA accelerators. Vitis environment enables the user to easily and productively develop accelerated algorithms and then efficiently implement and deploy them onto heterogeneous CPU-FPGA-ACAP systems. Vitis supports: C and C++ kernels. RTL design flows are also supported for experienced hardware developers. Each of these flows will be discussed along with the open-source Xilinx Runtime Library and Vitis open-source accelerated libraries. We will also introduce the PYNQ project and show how PYNQ makes the use of Xilinx accelerator much easier.   The latest available cloud and local hardware will be covered including AWS F1, and the range of Alveo accelerator boards. Topics to be covered:  

• Xilinx Vitis development framework, design flows, and use cases
• AWS and Alveo boards for FPGA acceleration
• Demonstration and hands-on-experience
• Vitis development flow
• Developing, profiling and optimizing applications for FPGA
• Using Xilinx accelerator in the cloud

Day 1

• Xilinx platforms
• Introduction to Vitis for accelerated platforms
• Vitis tool flow
• OpenCL execution model
• Vitis design analysis
• Get connected to AWS F1
• Hands-on: Vector Add lab

Day 2

• Vitis design methodology
• Host code optimization
• Kernel Optimization
• Vitis Accelerated Libraries
• Hands-on: Improving performance lab
• Hands-on: Optimization lab
• Hands-on: Vitis Accelerated libraries lab